1. Field
Embodiments of the invention generally relate to the processing of substrates, and more particularly relate to methods for forming tungsten materials on substrates using vapor deposition processes.
2. Description of the Related Art
For over 50 years, the number of transistors formed on an integrated circuit has doubled approximately every two years. This two-year-doubling trend, also known as Moore's Law, is projected to continue, with devices formed on semiconductor chips shrinking from the current critical dimension of 20-30 nm to below 100 Angstroms in future fabrication processes currently being designed. As device geometries shrink, substrate sizes also grow. As the 300 mm wafer replaced the 200 mm wafer years ago, the 300 mm wafer may be replaced by the 400 mm or 450 mm wafer.
As device dimensions continue to shrink, and the two-dimensional limitations of Moore's Law become insurmountable, manufacturers are turning to three-dimensional structures to propel future growth. Devices such as FinFETs and three-dimensional memory devices such as DRAM devices typically feature layers of different materials in a stack. Multiple devices or cells may be stacked one atop the other, and several devices are typically formed on one substrate. The layers are often different materials, so one structure may contain alternating layers of insulating, semiconducting, and metallic layers such as SiO2, SiN, a-Si, and poly-Si. Typically the stack consists of 32 or 64, or even 128 layers of these alternating layers.
Tungsten has been used at contact level in logic application for about two decades. In recent advanced CMOS devices, new technology such as metal gate and FinFET emerge, which leads to a new application for tungsten as metal gate fill for both PMOS and NMOS devices. In 3D NAND devices, tungsten is also used for metal gate fill. The requirement for tungsten fill becomes more and more challenging. For contact, the overhang becomes more challenging as the dimensions of contacts are getting smaller and typically leaves a big seam after tungsten conformal fill. Furthermore, the seam will be exposed to slurry during tungsten CMP, which causes integration issues. For metal gate trench in both advanced CMOS and 3D NAND, traditional tungsten conformal growth inevitably leaves a seam in the middle. In addition, the surface area of the trench or via of 3D NAND structure is significantly larger than the surface area of standard via/trench. Thus, fast deposition rate and insufficient reactant supply may lead to inconsistent thickness of the tungsten fill between high density and low density pattern areas. Therefore, an improved method of forming tungsten fill is required for both contact and metal gate fill in the advanced logic and memory devices.